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| vishay siliconix sic401a, SIC401BCD document n umber: 63 835 s12-2 109-re v. c, 03-sep-12 www.vishay.com 1 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 f o r techn i cal q uestions , contact: po w e r i ct echsuppor t@visha y .com 15 a microbuck ? sic401a/b integrated buck regulato r with programmable ldo descript ion the visha y sil i coni x sic4 01a/b an adv a n ced stand-a l one synchron ous b u c k re gul ator f eatur ing i n teg r ated po w e r mosfets , boo tstr ap s w i t ch, a nd a prog r a mma b le ldo in a space - sa ving p o w e rp ak mlp55-3 2l pin p a c k ages . the sic40 1 a/b is capa b le of ope r a ting w ith a ll cer a mic soluti ons an d s w i t chi ng frequ encie s up to 1 mhz. the prog ramma b le frequ ency , synch ro nou s op er a t i on and sele cta b le p o w e r-sa v e all o w ope r a tion at h i gh e f ficie n cy across the ful l r a nge of loa d current. th e in te r n a l ld o ma y be use d to supp ly 5 v f o r th e g a te dr iv e circui ts or it ma y be b y pa ssed with an e xter nal 5 v f o r op ti m u m effici ency and used to d r iv e e xte r n a l n - ch ann el mosfets or o t h e r l oads . additional f eat ures include cycle-b y-cycle current limit, v o l t a ge soft-star t, unde r-v o ltage protection, pro g rammab l e o v er-curren t protection, soft shu t do w n an d sel e ctab le po w e r-sa v e . the visha y sil i coni x si c401 a/b al so pro vide s an e nab l e inpu t an d a p o w e r go od ou tpu t . fe atures ? h igh efficien cy > 93 % ? 1 5 a con t in uou s ou tp ut curren t cap abil i ty ? i ntegra t e d bootstra p switch ? p rog r amma ble 200 ma ldo with b y p a ss log i c ? t empe ra tu re co mp ensated curre nt li mi t ? a l l ce ra mic so lution en abl ed ? p seu do fixed-frequ ency adap ti ve o n -time co ntrol ? p rog r amma ble in put uvlo thresho l d ? i nd epen den t ena ble pi n fo r switche r an d ldo ? s e l ectable u l tra - sonic pow er-save mo de (sic40 1 a) ? s el e cta b l e po w e r-sa ve mo de (sic 4 0 1 b ) ? p rog r amma ble soft-start and soft-sh utdown ? 1 % in te rn al reference vol t a g e ? p o w er good o u tput ? o ver-voltage a nd un der-voltag e p r otecti ons ? m ateria l catego ri zation: fo r d e finitio n s of comp lian c e pl e a se se e w ww.vi shay.com/d oc?99 912 applicat ions ? n ote boo k, desktop an d se rve r comp ute r s ? d igital hdtv and di gital consu m e r ap pli c a t i ons ? n etw o rking an d te lecommuni cation eq uipmen t ? p rin t e r s, dsl, a nd stb app licatio ns ? e mbe dded a ppl ications ? p oi n t of l o ad p o w er su pp l i e s typica l a p plic ation ci rcu it an d pa cka ge options product summary input voltage range 3 v to 17 v output voltage ra nge 0.6 v to 5.5 v oper ating f r equency 200 khz to 1 mhz contin uous outp ut current 1 5 a p eak efficiency 93 % p a c k age p o w erp ak mlp55-32 l typ i cal ap plication circuit fo r sic401a/b (powerpak mlp5x5-32l) pa d 1 a g n d lx pad 3 lx pad 2 v i n p g n d lx p g n d p g n d p g n d p g n d p g n d 17 1 8 19 20 21 t o n a g n d e n \ps v lx i lim p goo d bs t v i n fb l a g n d v dd v ou t fb 1 2 3 4 5 7 6 8 ss p g n d v i n v i n v i n n c lx n c 9 10 11 12 13 14 15 16 24 lx 23 22 e n l v i n v out v ou t p goo d e n /p s v (tri -s ta t e ) ldo_e n p g n d 31 30 2 9 2 5 26 27 2 8 32 http://
w ww.vishay.co m 2 document number: 63835 s12-2109-rev. c, 03-sep-12 vishay siliconix sic401a, SIC401BCD this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com functio n al bloc k d i ag ram pin configuration sic401a/b fu nctiona l block diagram reference soft star t fb agnd on - t ime gener at or control & status pgood gate drive control vin pgnd ton vout zer o cr oss det e ct or val l ey cur r ent li mi t il im enl fbl vldo switchover mux a y b ldo vdd bst fb comparator - lx en/psv bypass comparator bypass compar at or nc nc a 12 8 27 14 32 5 3 2 31 1 26 29 a = connect e d t o pi ns 6, 9 - 11 , pad 2 b = connect e d t o pi ns 23 -25 , pad 3 c = connect e d t o pi ns 15- 2 2 d = connect to pins 4, 30, pad 1 b c d v in vdd vdd v in boot st r a p switch lo- s i d e mosfet hi-side mosfet lxbst 13 lxs 28 dl dl vdd vdd vdd ss 7 sic401a/b pin configuration (top view) pa d 1 a g n d lx pa d 3 lx pa d 2 v i n p g n d lx p g n d p g n d p g n d p g n d p g n d 17 1 8 19 20 21 t o n a g n d e n \ps v lx i lim p good bs t v i n fb l a g n d v dd v ou t fb 1 2 3 4 5 7 6 8 ss p g n d v i n v i n v i n n c lx n c 9 10 11 12 13 14 15 16 p g n d 24 lx 23 22 e n l 31 30 2 9 2 5 26 27 2 8 32 document n umber: 63 835 s12-2 109-re v. c, 03-sep-12 www.vishay.com 3 vishay sili conix sic401a, SIC401BCD th is d o c u m e n t i s su bj ec t t o c h an ge with o u t no tic e . the pr oduc t s descri bed herei n and t h is document ar e subject t o speci fic di sclai m ers , set for t h a t www .v is ha y . co m/ do c? 91 00 0 f o r techn i cal q uestions , contact: po w e r i ct echsuppor t@visha y .com form at : line 1: p/n line 2: sil i coni x lo go + lo t code + esd symbol line 3: factory code + year code + work week code pin descript ion pin num b er sym b o l d escription 1f b f ee dbac k input f or s w itching regulator used to prog r am the outpu t v olta ge - co nnect to an e x ter nal resistor divider from v out to a gnd . 2v out switcher output v oltage sense pin - also th e inp ut to the inter nal s w itch-o v er be tw e en v out an d v ldo . the v o ltag e at this pin m u st be le ss than or equal to the v o ltage at the v dd pin. 3v dd bia s sup ply f or the i c - w hen u s ing the inter nal ld o as a bias po w e r supply , v dd is the ldo outp u t. when using an e x ter n al po w e r supply as the bias f o r the ic , the ldo outpu t shou ld be disab l ed. 4, 3 0 , p a d 1 a gnd analog g r ound 5f b l f ee dbac k inp ut f or the inter nal ldo - used to prog r am the ldo outpu t. conne ct t o an e x ter nal resistor divider from v dd to a gnd . 6, 9 to 11, p a d 2 v in input supply v o ltage 7 s s t he soft star t r amp will be pro g r amme d b y an inte r nal current source chargin g a capacitor on this pin. 8b s t bootstr ap pin - connect a capacitor o f at least 100 nf from bst to lx to d e v elop th e floating supp ly f o r the hig h -side g a te dr iv e . 12, 14 nc no connection 13 lxbst lx boost - connect to the bst c apa c i tor . 23 to 25, p a d3 lx switching (phase) node 15 to 22 p gnd p o w e r g r ound 26 p goo d open-dr a i n po w e r good in dicator - high impedan ce in dicates po w e r is goo d. an e x ter n al pull-up resistor is re quired. 27 i lim current limit sense pin - used to prog r a m t he current limit b y connecti ng a resistor from i li m to lxs . 28 lxs lx sense - connects to r il im 29 en/psv enab le/po w er sa v e inpu t f o r the s w itching regulator - connect to a gnd to disab l e the s w itching reg ulator , connect to v dd to oper a t e with po w er-sa v e mode and flo at to op er ate in f orced cont in uous mode . 31 t on on-time prog r a mming input - set th e on-time b y connectin g through a resistor to a gnd 32 e n l enab le input f o r th e ldo - co nnect enl to a gnd to disab l e the ld o . dr iv e with logic signal f o r log i c control, or p r og r am the v in uvlo with a resistor divider bet w e e n v in , enl, and a gnd . or derin g i n forma t i o n p a r t num b er p a c k a g e m a r ki ng (lin e 1: p/n ) sic 401a cd-t1-ge3 p o w e rp ak mlp55-32l sic401a sic 401bcd-t1-ge3 p o w e rp ak mlp55-32l sic401b sic 401db ref e rence b oard w ww.vishay.co m 4 document number: 63835 s12-2109-rev. c, 03-sep-12 vishay siliconix sic401a, SIC401BCD this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com stresses beyond those listed under "absol ute maximum ratings" may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condi tions beyond those indicated in the operational sections of t he specifications is not implied. exposure to absolute maximum rating/condi tions for extended periods may affect device reliability. ab so lu te ma ximum ratin gs (t a = 25 c , un le ss ot he rw is e no te d) elect rical p a ramet e r co nd itio ns lim i ts unit v in to p gnd - 0.3 to + 20 v v in to v dd - 0.4 max. lx to p gnd - 0.3 to + 20 lx (t r ansient < 100 ns) t o p gnd - 2 to + 20 v dd to p gnd - 0.3 to + 6 en/psv , p good , i lim r ef erence to p gnd - 0.3 to + (v dd + 0.3) t on to p gnd - 0.3 to + (v dd - 1.5 ) bst to lx - 0.3 to + 6 to p gnd - 0.3 to + 25 enl - 0.3 to v in a gnd to p gnd - 0.3 to + 0.3 t e mp erature maxim u m j u n c tion t e mper ature 150 c stor age temperature - 65 to 150 p o we r d i s s i pa t i on j unction to ambient the r mal impedan ce (r thj a ) (b ) ic section 50 c / w maxim u m p o w e r dissipation ambient t e mper ature = 2 5 c 3.4 w ambient t e mper ature = 1 00 c 1.3 esd pr otection hbm 2 kv reco mmended opera t in g c ond itions ( a ll v o lt ag es re fer e n c e d to g n d = 0 v) p a ram e ter symb ol min. t y p. max. unit inpu t v o ltage v in 31 7 v v dd to p gnd 35 . 5 output v oltage v out 0.6 5.5 t e mp erature ambient t emper ature - 40 to 85 c document n umber: 63 835 s12-2 109-re v. c, 03-sep-12 www.vishay.com 5 vishay sili conix sic401a, SIC401BCD th is d o c u m e n t i s su bj ec t t o c h an ge with o u t no tic e . the pr oduc t s descri bed herei n and t h is document ar e subject t o speci fic di sclai m ers , set for t h a t www .v is ha y . co m/ do c? 91 00 0 f o r techn i cal q uestions , contact: po w e r i ct echsuppor t@visha y .com ele c trical specifications p a rameter s y mbol t e st co nd ition s un less spec ified v in = 12 v , v dd = 5 v , t a = + 25 c f o r typ ., - 40 c to + 85 c f o r min. a nd max. , t j = < 125 c , typical application circuit min. t y p. max. unit inp u t p o wer su ppli e s input supply v o ltage v in 31 7 v v dd v dd 35 . 5 v in u v l o t h reshold (a ) v uvlo sen s ed a t e n l pin, r i sing 2.4 2.6 2 . 95 s e nsed at enl pin, f alling 2.23 2.4 2 . 57 v in uv lo hy st e r e s is v uvlo , hys 0.25 v dd uvlo threshold v uvlo mea s ured at v dd pin, r i sing 2.5 3 measured at v dd pin, f a lling 2 .4 2 . 9 v dd uvlo hysteresis v uvlo , hys 0.2 v in supp ly current i in enl, en/psv = 0 v , v in = 17 v 10 20 a standb y mode; en l= v dd , en/psv = 0 v 130 v dd supply current i dd enl, e n /ps v = 0 v 190 300 si c 4 0 1 a, en / p sv = v dd , no load (f sw = 25 khz), v fb > 0.6 v (b ) 0.3 ma sic401b , en/psv = v dd , no load, v fb > 0.6 v (b ) 0.7 v dd = 5 v , f sw = 250 khz, en/psv = fl oating, no l oad (b ) 9 v dd = 3 v , f sw = 250 khz, en/psv = fl oating, no l oad (b ) 5.5 fb on-t ime thre shold s tatic v in and load 0.594 0.600 0. 606 v f r equency r ange f sw cont in uous mode operation 1000 kh z mini m u m f sw , (sic4 01a only) 25 bootstr ap switch r e sistance 10 ? tim i ng on- t ime t on cont in uous mode operation v in = 12 v, v out = 5 v , f sw = 300 khz, r ton = 133 k ? 999 1110 1220 ns mi n i m u m on-ti me (b ) t on , mi n. 80 mi n i m u m off-ti me (b ) t off , min. v dd = 5 v 250 v dd = 3 v 370 soft star t soft star t cur r ent (b ) i ss 3 a soft star t v o ltage (b ) v ss when v out re aches re gulation 1 .5 v an alog inpu ts/o u t pu ts v out i nput resistance r o- in 500 k ? cu r r en t sen s e zero-crossing detector thresho l d v o ltage v s ense - th lx-p gnd - 3 + 3 mv po w e r g o o d p o w e r good threshold pg_v th_upper u pper limit, v fb > inter nal 60 0 mv ref e rence 20 % pg_v th_lo we r lo w e r limit, v fb < int e r n a l 60 0 mv ref e rence - 10 star t-up d ela y t i me (betw e e n pwm e nab le and p good high) pg _ t d v dd = 5 v , c ss = 10 nf 12 ms v dd = 3 v , c ss = 10 nf 7 f ault (noise-imm unity) dela y time (b) pg_i cc 5 s leakage current pg_i lk 1 a p o w e r good on-resistance p g_r ds_on 10 ? f a ult pr ote c tio n v a lle y current limit i lim v dd = 5 v, r ilim = 394 5, t j = 0 c t o +125 c 12.75 15 17 .25 a v dd = 3.3 v , r ilim = 3945 13.5 i lim source current 10 a w ww.vishay.co m 6 document number: 63835 s12-2109-rev. c, 03-sep-12 vishay siliconix sic401a, SIC401BCD this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com no t e s : a. v in uvlo is programmable using a resistor d i vide r fro m v in to enl to a gn d . t he enl voltage is compared to an internal referen c e. b. t y pical value measured o n stan dard evaluation board . c. sic401a/b has first order tempera t ure compensation for over current. r e sult s va ry based upon the pcb th ermal layout d. t he sw itch-o ver threshold is the maximum voltage dif f erential b etween the v ldo and v out pins w h ich ensures that v ldo wil l inter nally switch -over to v out . the non-switch-over thre shold is the minimum voltage diff erential betwe en the v ldo and v out pins wh ich ensures that v ldo w i ll no t switch-over to v ou t . e. t he ldo dro p out voltag e is the voltage at which the ldo outpu t drops 2 % belo w the nominal regulation point. i li m comparator offset v o ltage v ilm- lk with respect to a gnd - 10 0 + 10 mv output u nder-v oltage f ault v ouv_f a ul t v fb with respect to inter nal 600 mv ref e rence , 8 con s ecutiv e cloc ks - 25 % smar t p o w e r-sa v e protection t h reshold v o ltage b p sa v e_vth v fb with respect to inter n al 600 mv + 10 ov er-v oltage protect i on t h reshold v fb with respect to inter n al 600 mv + 20 ov er-v oltage f ault dela y b t ov - d e l a y 5 s ov er t e mperature shutdo wn b t shut 10 c h y ste r esis 1 5 0 c lo gi c i n pu t s / o ut p ut s log ic input high v o ltage v ih 1 v log ic input lo w v o latge v il 0.4 en/psv input f o r p-sa v e oper ation (b ) v dd = 5 v 2 . 2 5 en/psv input f o r f o rced contin uous oper ation (b ) 12 en/psv input f o r disab l i ng sw i t cher 00 . 4 en/psv input b i as current i en - 10 + 10 a enl i nput bias current i enl 81 5 f b l, fb input b i as current fbl_i lk - 1 + 1 l i near dr opo ut regu lato r fbl (b) v ldo a c c 0.75 v ld o cu rren t limit l d o _i li m shor t-circuit protection, v in = 12 v , v dd < 0.75 v 65 ma star t-up and f o ldbac k, v in = 12 v , 0. 75 < v dd < 90 % of final v dd va l u e 11 5 op er ating current limit, v in = 12 v , v dd > 90 % o f final v dd va l u e 135 2 00 v ldo to v out sw it c h - o v e r t h res h ol d (d ) v ldo-bps - 130 + 130 mv v ldo to v out non-s w itch-o v e r t h reshold (d ) v ldo- nbps - 500 + 500 v ldo to v out switc h - o v e r resi stance r ldo v out = 5 v 2 ? ld o drop out v oltage (e ) fr o m v in to v dd , v dd = + 5 v , i vl d o = 100 ma 1.2 v e l ect r ical spe cificat i ons p a rameter symbol test conditio ns u n less sp ecified v in = 12 v , v dd = 5 v , t a = + 25 c f o r typ ., - 40 c to + 85 c f o r min. and max., t j = < 125 c , t y pica l app lication circuit mi n. t y p. ma x. un i t vishay siliconix sic401a, SIC401BCD document number: 63835 s12-2109-rev. c, 03-sep-12 www.vishay.com 7 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com e l ec tr ica l c h ar ac te ri st ic s effiency/po we r l o ss vs. lo ad p-sav e (v dd = 3.3 v, v out = 1.5 v , sic 401b) effiency/po we r l o ss vs. lo ad p-sav e (v dd = 5 v, v out = 1.5 v, sic401b ) effiency/power loss vs. load fcm (v dd = 5 v, v out = 1.5 v, sic401b) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 50 55 60 65 70 75 80 85 90 95 100 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 p l o ss( w ) e? c i e n c y ( % ) i ou t (a ) v in =5v v in =12v v in =12v v in =5v vin=17v v in =17v 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 50 55 60 65 70 75 80 85 90 95 100 0 1 2 3 4 5 6 7 8 9 1 01 11 21 31 41 5 p lo s s (w ) e? c ie n c y ( % ) i ou t (a ) v in =12v v in =5v v in =17v v in =12v v in =5v v in =5v v in =5v v in =5v v in =5v v in =5v vin=17v p l o ss (w) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 50 55 60 65 70 75 80 85 90 95 100 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 e ?ci e nc y ( % ) i ou t (a ) v in =5v v in =12v v in =12v v in =5v v in =17v v in =17v effien cy/power lo ss-p-sav e vs. fc m (v dd = 3.3 v, v out = 1.5 v, v in = 12 v, sic 401b) effien cy/power lo ss-p-sav e vs. fc m (v dd = 5 v, v out = 1.5 v, v in = 12 v, sic401b) effien cy/power lo ss-p-save (v out = 1.5 v, v in = 12 v, sic 401b) -0 . 1 -0 . 0 5 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 50 55 60 65 70 75 80 85 90 95 0 1 2 3 4 5 6 7 8 9 1 01 11 21 31 41 5 p l o ss (w ) e ?ci e n c y (%) i ou t (a ) psav e fcm fcm minus psm -0. 1 -0 . 0 5 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 50 55 60 65 70 75 80 85 90 95 100 0123456789 1 0 1 1 1 2 1 3 1 4 1 5 p lo s s (w ) e? c i e n c y ( % ) i ou t (a ) psav e fcm fc m minus psm -0 .15 -0. 0 5 0.05 0.15 0.25 0.35 50 55 60 65 70 75 80 85 90 95 100 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 p l os s (w ) e? c i e n c y ( % ) i ou t (a ) 3.3v b i a s 5v bias 3. 3v minus 5v w ww.vishay.co m 8 document number: 63835 s12-2109-rev. c, 03-sep-12 vishay siliconix sic401a, SIC401BCD this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com e l ectrical characteristics lo a d r e g ul a t i on - f c m (v dd = 5 v, v out = 1.5 v, sic4 01b) lo ad regu latio n - p-save (v dd = 5 v, v out = 1.5 v, sic4 01b) s w itchin g freq uen cy - p-save mod e vs. f c m (v dd = 5 v, v out = 1.5 v , v in = 12 v, sic401 b) 1.4 1.41 1.42 1.43 1.44 1.45 1.46 1.47 1.48 1.49 1.5 1.51 1.52 1.53 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 v ou t (v ) i ou t (a ) v in =5v =12v in v 1.4 1.41 1.42 1.43 1.44 1.45 1.46 1.47 1.48 1.49 1.5 1.51 1.52 1.53 0123456789 1 0 1 1 1 2 1 3 1 4 1 5 v ou t (v ) i ou t (a ) v in =5 v v in =12v 0 50 100 150 200 250 300 350 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 s w i tc h i n g f r eq u en c y( k hz ) i ou t (a ) fcm ps av e lo a d re g ul a t i on - f c m (v dd = 3.3 v, v out = 1.5 v, sic401b ) l o ad reg u lati on - p-save (v dd = 3.3 v, v out = 1.5 v, sic401b ) switch ing frequ e ncy - p-save vs. fcm (v dd = 3.3 v, v out = 1.5 v, v in = 12 v, sic401b) 1.4 1.41 1.42 1.43 1.44 1.45 1.46 1.47 1.48 1.49 1.5 1.51 1.52 1.53 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 v ou t (v ) t (a ) v in =5 v v in =1 2 v 1.4 1.41 1.42 1.43 1.44 1.45 1.46 1.47 1.48 1.49 1.5 1.51 1.52 1.53 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 v ou t (v ) i ou t (a ) v in =5 v v in = 12v 0 50 100 150 200 250 300 350 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 s w itc h in g fre q u e n c y ( k h z ) i ou t (a ) fcm psave fcm psave vishay siliconix sic401a, SIC401BCD document number: 63835 s12-2109-rev. c, 03-sep-12 www.vishay.com 9 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com e l ec tr ica l c h ar ac te ri st ic s load reg u lat i on vs. tem p erat ure - fcm (v dd = 5 v, v out = 1.5 v, sic401b ) loa d reg u lation vs. tem p erature - p - save (v dd = 5 v, v out = 1.5 v, sic401b ) effiency variation with v out - p-save (v dd = 5 v, v in = 12 v, l = 2.2 h (4.6 m ? ) for v out = 2.5 v, 3.3 v and 5 v, sic401b) 1.45 1.46 1.47 1.48 1.49 1.5 1.51 1.52 1.53 0123456789 1 0 1 1 1 2 1 3 1 4 1 5 v ou t (v ) i ou t (a ) v in =12v,t a =25 v in =5v,t a =25 c v in =12v,t a = - 40 c v in =5v,t a =- 40 c v in =12v,t a =85 c v in =5v,t a =85 c 1.45 1.46 1.47 1.48 1.49 1.5 1.51 1.52 1.53 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 v ou t (v ) i ou t (a ) v in =12v,t a =25 v in =5v,t a =25 c v in =12v,t a =-40 c v in =5v,t a =- 40 c v in =12v,t a =85 c v in =5v,t a =85 c 75 80 85 90 95 100 0123456789 1 0 1 1 1 2 1 3 1 4 1 5 e ? c ie n c y ( % ) i ou t (a ) v out= 1.5v v out =1v v out =3.3v v out =5v v out =2.5v lo ad reg u lation vs. te mpe r a t ure - p-save (v dd = 3.3 v , v out = 1.5 v, sic401b) loa d reg u lat i on vs. tem p erat ure - fcm (v dd = 3.3 v , v out = 1.5 v, sic401b) efficiensy/power loss vs. p-save (v out = 1.5 v, v in = 12 v, sic401b) 1.45 1.46 1.47 1.48 1.49 1.5 1.51 1.52 1.53 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 v ou t (v ) i ou t (a ) v in =12v,t a =25 v in =5v,t a =25 c v in =12v,t a =-40 c v in =5v,t a =- 40 c v in =12v,t a =85 c v in =5v,t a =85 c 1.45 1.46 1.47 1.48 1.49 1.5 1.51 1.52 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 v ou t (v ) i ou t (a ) v in =12v,t a =25 v in =5v,t a =25 c v in =12v,t a =-40 c v in =5v,t a =- 40 c v in =12v,t a =85 c v in =5v,t a =85 c 0 0. 05 0. 1 0. 15 0. 2 50 55 60 65 70 75 80 85 90 95 0. 001 0. 01 0. 1 1 10 100 p lo s s (w ) e? c i e n c y ( % ) i ou t (a ) external bias ldo bias ldo minus external w ww.vishay.co m 10 document number: 63835 s12-2109-rev. c, 03-sep-12 vishay siliconix sic401a, SIC401BCD this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com e l ectrical characteristics effien cy/power l o ss vs. l o ad - p-s a ve (v dd = 3.3 v, v out = 1.5 v, sic401a ) e f fien cy/power lo ss - p-save vs. f c m (v dd = 5 v, v out = 1.5 v , v in = 12 v, sic401 a) effiency/power loss vs. load - p-save (v dd = 5 v, v out = 1.5 v, sic401a) p loss (w) 0 0. 5 1 1. 5 2 2. 5 3 3. 5 4 4. 5 5 50 55 60 65 70 75 80 85 90 95 100 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 e ? ci e n cy(%) i ou t (a ) v in =5v v in =12v v in =17v v in =17v v in =12v v in =5v -0.1 -0 . 0 5 0 0. 05 0. 1 0. 15 0. 2 0. 25 0. 3 50 55 60 65 70 75 80 85 90 95 100 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 e ? ci e n cy(%) i out (a ) psave fcm fcm minus psm p loss (w) 0 0. 5 1 1. 5 2 2. 5 3 3. 5 4 4. 5 5 50 55 60 65 70 75 80 85 90 95 100 0123456789 1 0 1 1 1 2 1 3 1 4 1 5 p lo s s (w ) e? c i e nc y ( % ) i ou t (a ) v in -5v v in =12v v in =17v v in =5v v in =12v v in =17v effien cy/power lo ss - p - save vs. f c m (v dd = 3.3 v, v out = 1.5 v, v in = 12 v, sic401a) effien cy/power lo ss - p - save (v out = 1.5 v, v in = 12 v, sic401a) load regulation - p-save (v dd = 5 v, v out = 1.5 v, sic401a) -0.1 -0 . 0 5 0 0. 05 0. 1 0. 15 0. 2 0. 25 0. 3 0. 35 0. 4 50 55 60 65 70 75 80 85 90 95 100 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 p lo s s (w ) e ? ci e n cy(%) i ou t (a ) psave fcm fcm minus psm -0.15 -0 . 1 -0 . 0 5 0 0. 05 0. 1 0. 15 0. 2 0. 25 0. 3 50 55 60 65 70 75 80 85 90 95 100 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 p lo s s (w ) e? c i e n c y ( % ) i ou t (a ) 3.3v bias 3.3v minus 5v 5v bias 1.445 1. 455 1. 465 1. 475 1. 485 1. 495 1. 505 1. 515 1. 525 0123456789 1 0 1 1 1 2 1 3 1 4 1 5 v ou t (v ) i ou t (a ) v in =12v v in =5v vishay siliconix sic401a, SIC401BCD document number: 63835 s12-2109-rev. c, 03-sep-12 www.vishay.com 11 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com e l ec tr ica l c h ar ac te ri st ic s lo ad r e gul ation - p-save (v dd = 3.3 v, v out = 1.5 v , sic 401a) loa d reg u lation vs. tem p erature - p - save (v dd = 5 v, v out = 1.5 v, sic401a ) star t- up - e n / p s v (v dd = 5 v, v in = 12 v, v out = 1.5 v, i out = 0 a, sic401b) 1.445 1. 455 1. 465 1. 475 1. 485 1. 495 1. 505 1. 515 1. 525 1. 535 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 v ou t (v ) i ou t (a ) v in =12v v in =5v 1.445 1. 455 1. 465 1. 475 1. 485 1. 495 1. 505 1. 515 1. 525 1. 535 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 v o ut (v ) i ou t (a ) v in =12v,t a =25 c v in =5v,t a =25 c v in =5v,t a =-40 c v in =5v,t a =85 c v in =12v,t a =85 c v in =12v,t a =-40 c time(1ms/div) (5v/div) (1v/div) (500mv/div) (5v/div) en/psv vout ss lx lo ad reg u lation vs. te mpe r a t ure - p-save (v dd = 5 v, v out = 1.5 v, sic401a ) shutdow n - en/psv (v dd = 5 v, v in = 12 v, v out = 1.5 v, i out = 5 a, sic401b) 1.445 1. 455 1. 465 1. 475 1. 485 1. 495 1. 505 1. 515 1. 525 1. 535 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 v ou t (v ) i ou t (a ) v in =12v,t a =25 c v in =5v,t a =25 c v in =5v,t a =-40 c v in =5v,t a =85 c v in =12v,t a =85 c v in =12v,t a =-40 c (5v/div) (1v/div) (500mv/div) (5v/div) time(50 s/div) ss lx vout en/psv w ww.vishay.co m 12 document number: 63835 s12-2109-rev. c, 03-sep-12 vishay siliconix sic401a, SIC401BCD this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com e l ectrical characteristics start-up (pr e -bias) - en/psv (v dd = 5 v, v in = 12 v, v out = 1.5 v, i out = 0 a , sic401b) po we r - save mod e (v dd = 5 v, v in = 12 v, v out = 1.5 v, i out = 0 a , sic401a) t r ansie n t r espo n se - p-save l o ad rising (v dd = 5 v, v in = 12 v, v out = 1.5 v, i out = 0 a to 11 a, sic401b, di/dt = 1 a/s) time(1ms/div) (5v/div) (1v/div) (500mv/div) (5v/div) en/psv vout ss lx (5v/div) (100 mv/div) time (20 s/div) vout ripple lx (5v/div) (50mv/div) iout :0a-11a vout ripple lx (4a/div) time(10 s/div) p o wer-save mo de (v dd = 5 v, v in = 12 v, v out = 1.5 v , i ou t = 0 a, sic401b ) f o rced con t in uo us mo de (v dd = 5 v, v in = 12 v, v out = 1.5 v, i ou t = 15 a, sic401b ) t r ansie n t r espo n se - p-save l o ad fallin g (v dd = 5 v, v in = 12 v, v out = 1.5 v, i out = 11 a to 0 a, sic401b, di/dt = 1 a/s) (5v/div) (50mv/div) time(10ms/div) vout ripple lx (5v/div) (50mv/div) vout ripple lx swit ching mode time(5 s/div) (5v/div) (4a/div) (50mv/div) time(10 s/div) lx iout :11a to 0a vout ripple vishay siliconix sic401a, SIC401BCD document number: 63835 s12-2109-rev. c, 03-sep-12 www.vishay.com 13 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com e l ec tr ica l c h ar ac te ri st ic s tran sient resp ons e - f c m (v dd = 5 v, v in = 12 v, v ou t = 1.5 v, i out = 0 a to 11 a, sic401b, di/dt = 1 a/s) t r an sien t resp on se - p-save lo ad ri sing (v dd = 5 v, v in = 12 v, v ou t = 1.5 v, i out = 0 a to 11 a, sic401a, di/dt = 1 a/s) over current protection-under voltage prodection (v dd = 5 v, v in = 12 v, v out = 1.5 v, sic401b) (5v/div) (4a/div) (50mv/div) iout :0a t o 11a lx time(20 s/div) vout ripple (5v/div) (100mv/div) vout ripple iout :0a to 11a lx (4a/div) time(10 s/div) time(100 s/div) (5v/div) (5v/div) (5v/div) (500mv/div) (5a/div) pgood vout induc tor lx ove r t e mp eratu r e shutdo wn at 133 .4 c (v in = 12 v , v out = 1.5 v , i ou t = 0 a, ld o mo de, sic4 01b) t r an sien t resp on se - p-save lo ad f a lling (v dd = 5 v, v in = 12 v, v out = 1.5 v, i out = 11 a to 0 a, sic401a, di/dt = 1 a/s) (5v/div) (2v/div) pgood lx time(500 s/div) (5v/div) vout ripple time(20 s/div) (4a/div) (100mv/div) lx iout : 0a to 11a w ww.vishay.co m 14 document number: 63835 s12-2109-rev. c, 03-sep-12 vishay siliconix sic401a, SIC401BCD this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com ope r ational de scription d evice ov erv i e w the sic40 1 a/b is a step down synchro nous dc/dc b u ck co nverter wi th i n te grated po wer mosfets a nd a 2 00 ma ca pab le p r ogrammab l e l d o. the device is ca pabl e o f 15 a ope rati on at very hi gh effici ency. a spa c e savin g 5 x 5 (mm) 32- p in package is used. the programmable o peratin g frequ ency o f up to 1 mhz en abl es op ti mi zing th e co nfi guratio n fo r pcb area an d effici ency. the buck controlle r use s a ps eud o-fi xed freq uen cy ada ptive o n -ti m e con t rol . th is con t rol method al lows fa st tran sient i gpon se which pe rmi t s th e use of smal ler output capaci t o r s. input voltage require m ents the sic4 01a/b req u ires two inpu t supp lies for n o rma l o peratio n: v in an d v dd . v in opera t e s o v e r a wide ra nge from 3 v t o 17 v. v dd requi res a 3 v to 5.5 v su pply in put th at ca n b e a n e x te rn al source or the in te rn al ldo con f i gured to su pply 3 v to 5.5 v from v in . power up sequence w hen the si c401 a/b uses an e x te rn al po wer source at th e v dd pin, the switchin g reg u la tor initia te s th e start up whe n v in , v dd , and en/psv are ab ove their respec tive thresholds. when en/psv is at logic high, v dd nee ds to be a ppli ed a f ter v in rises. it i s a l so recommend ed to use a 10 ? resistor b e tween a n exte rnal po wer source and the v dd pi n. to start up by using the en/psv pin when both v dd an d v in are a bove the i r respe c tive th reshol ds, appl y en/psv to e nabl e the start-u p p r o c ess. fo r sic4 01a/b in self-bi a sed mode, re fer t o the l do sect ion f o r a fu ll descrip tio n . shutdown the sic40 1 a/b can be sh ut- down by p u lli ng either v dd or en/psv below its threshold. wh en us ing an external power so urce, i t is recommend ed that th e v dd vo lta ge ramps do wn before the v in voltag e. wh en v dd is active and en/psv at l ogic low, the output vol t a ge d i scharg e s in to th e v out pi n throu gh an in te rnal fet. ps eudo-fix ed freque ncy a d aptive on-time control the pw m co ntro l method u s ed by the sic 401a/b is p seudo - fi xed freq uency, ad aptive on-time, as sh own i n fig u re 1. the ripp le voltag e gene rate d at the ou tp ut cap a citor esr is used as a pwm ramp sign al. th is rip p le is use d to trigg e r the o n -ti m e o f the controll er. the ada ptive on -ti m e is de te rmi ned by an interna l on e- shot timer. w hen the one-sho t is trig g e red by the outpu t rippl e, the de vi ce se nd s a si ng l e on -t im e p u l se t o th e hi g h - sid e mosfet. th e p u lse perio d i s de termin ed by v out and v in ; the pe riod is propo rtio nal to o u tput vo lta ge and in versely p r opo rtio nal to inp u t voltage . with thi s ada ptive on-time a rrange me nt, the devi ce a u tomaticall y a n ti cipates the o n -time ne eded to regul ate v out fo r th e presen t v in co nditio n and at th e se lected freque ncy. the a d vantage s o f ada ptive on-time control are: ? p red i ctable o peratin g fre quen cy comp ared to other va ri abl e freq uency methods. ? r educe d compon ent count by el iminatin g th e error a m p lifier an d co mp ensatio n compone nts. ? r educe d compo nent co unt by re mo ving the ne ed to se nse a nd control in ductor cu rrent. ? f ast tra n sien t resp onse - the re sponse ti me is controll ed b y a fa st co mparator i n stead of a typ i call y slow error a m p lifier. ? r educe d o u tput cap a citance du e to fa st tran sient re sp onse . one-shot tim e r and opera t ing fr equency the on e-shot timer ope rates a s show n i n fig u re 2. the fb c o mparator output g oes h i gh when v fb is less than the i n ternal 60 0 mv refere nce. this fee d s in to the g a te d r i ve a n d turn s o n the hi gh-sid e mosfet, a nd a l so sta r ts the o ne-shot timer. the on e-shot timer uses an interna l co mp arator a nd a ca pacitor. one comparator inpu t is con nected to v out , the o t h e r inp u t i s co nnected to the cap a citor. when th e on-time b egi ns, the in tern al capa cito r cha r ges fro m zero vol t s thro ugh a current w h ich is p r oportio nal to v in . w hen the ca pacitor voltage reach e s v out , the on-time is completed a nd the hig h -side mosfet turns off. figu re 1 - o u tpu t rip p le a nd pw m co nt rol met hod v i n c i n v lx q1 q2 l esr + fb v lx t o n v fb c out v out fb threshold vishay siliconix sic401a, SIC401BCD document number: 63835 s12-2109-rev. c, 03-sep-12 www.vishay.com 15 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com this method automaticall y produ ces an o n -ti m e th at is prop ortiona l to v ou t a nd inversel y prop orti onal to v in . unde r steady-state con d ition s , the sw itch ing freq uen cy ca n be de te rmin ed fro m the on -time by the fo llo wing eq uation . the si c401 a/b u s es an external resistor to se t th e on ti me whi c h ind irectly se ts the frequ ency. the o n -time can be prog ramme d to provid e op erating fre que ncy up to 1 mhz usin g a resistor b e tween the t on p i n and grou nd. the resisto r valu e is se lected by th e fo llow ing eq uation . the constant, k, equals 1, w hen v dd is greater than 3.6 v. if v dd i s l e ss than 3 . 6 v an d v in is greate r than (v dd -1.75 ) x 10, k i s show n by the fol l ow i ng equation. the maxi mu m rton val ue a llo wed is show n by the follo wing eq uation . v out volt ag e select ion the switcher ou tp ut vo ltage i s reg u la te d by comparin g v out as seen throug h a resistor divid e r at the fb pi n to th e i n ternal 60 0 mv reference vol t a ge, se e fig u re 3. no te that thi s con t rol method reg u la tes the valle y of the ou tp ut ri pple voltage , n o t th e dc val ue. th e dc o u tput vol t ag e v out is offset by the outpu t ripp le accordi ng to the foll owin g e qua ti on. w hen a la rge ca pacitor i s pla ced i n p a ralle l wi th r1 (c top ) v out is sh own by th e fo llowi ng eq uation . enable and power-sa ve inputs the en/psv in put is u sed to e nab le or disab l e the switching reg u lator. when en/psv i s low (groun ded ), the switching reg u lator is off an d in its lowe st pow er state. whe n of f, the ou tp ut of th e switchin g reg u lator soft-discha r g e s the o u tput in to a 15 ? i n ternal resistor via th e v out pin. when en/psv is al lowe d to floa t, th e pin voltag e will floa t to 33 % of the vol t ag e at v dd . the swi t chi ng reg u lator turns on w i th po wer-save d i sable d an d all sw itch ing is in forced co nti nuo us mode . when e n /psv is h i gh (above 44 % of th e vol t a ge a t v dd ), the switchin g regul ator turn s on wi th p ower-save en abl ed. the si c401 a/b p-save ope ra ti on re duces the switching frequ ency accordi ng to the l oad for in cre a sed efficie n cy at li ght l oad con d ition s. fo rced con t in uo us mo de o p erati o n the si c401 a/b o perates the switcher i n fcm (forced continuous mode) by floating the en/psv pin (see figure 4). in this mode one o f the powe r mosfets i s alwa ys o n , w ith no in te ntiona l d ead time o t h e r than to avoid cross- con duction . thi s feature results i n uniform frequ ency across the fu ll loa d ra nge with th e trad e-off bei ng poo r efficien cy at li ght l oad s du e to the hi gh-freque ncy swi t ch ing of the mosfets. dh is ga te sign al to drive uppe r mosfet. dl is lo wer gate sign al to d r i ve lower mosfet fi g u r e 2 - on -t i m e g e ne ra t i on f igu re 3 - outpu t voltage sele ctio n fb v ref - + v out v i n r ton on-time = k x r ton x ( v out/ v i n ) fb compar ator one-shot timer gate dr i v es dh dl q1 q2 l q1 esr fb v out c out v lx + f s w = v out t o n x v i n r ton = 25 pf x f s w k (v dd - 1.75) x 10 v i n k = r ton_max = v i n _mi n 15 a v out r 1 r 2 t o fb pin v out = 0.6 x 1 + r 1 r 2 v ripple 2 + v out = 0.6 x 1 + r 1 r 2 v ripple 2 +x r 2 x r 1 r 2 + r 1 c top 1 + 2 1 + (r 1 c top ) 2 w ww.vishay.co m 16 document number: 63835 s12-2109-rev. c, 03-sep-12 vishay siliconix sic401a, SIC401BCD this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com ul traso n ic p o w e r-save op eratio n (sic401a) the sic 401a pro v ides ul tras o n ic pow er-save ope rati on at l ight lo ads, with the mi nimum op erating fre quen cy fi xe d at sl ightly und er 25 khz. this is accomplish ed by using a n internal timer that m o nitors th e ti me be tw e e n co ns ecu t i v e h i gh-si de gate pul ses. if th e time excee d s 4 0 s, d l drives h i gh to tu rn the l o w-side mosfet on . this draws current from v out throug h th e indu cto r , fo rcing both v out a nd v fb to fall . w hen v fb dro p s to the 600 mv thresho l d, th e next dh (the drive sig nal for the hig h side fet) on-time is trigg e red. after the o n -ti m e i s compl e ted th e high -side mosfet is turne d off and the lo w-side mosfet turns on . the low-sid e mosfet remai n s on until the in ductor cu rre n t ramps do wn to zero, at wh ich poi nt the low - si de mosfet is turn ed off. be ca use the o n -times are forc ed to occur at interval s n o g r eater than 40 s, the freque ncy wil l n o t fa ll fa r bel ow 2 5 kh z. fi gure 5 show s ul traso n ic powe r -sa ve o pera t io n. power-save ope r ation (sic40 1b) the sic 401b pro v i des po wer-save ope rati on at ligh t lo ads w i th n o min i mum op erating freque ncy. wi th po wer-save e nab led, th e interna l ze ro cro s si ng comparator moni tors the i ndu ctor cu rre n t vi a the vol t a ge acro ss the low-sid e mosfet d u ring the o f f-time. if the indu cto r current fall s to zero for 8 c o nsecutive switching cycles, the contr o ller enters mosfet on each subs equent cycle provided that the p o wer-save o pera t io n. it will turn o f f th e low-si de mosfet o n e a ch s u bsequ ent cycle provi ded th at the c u rrent crosses zero. a t this time both mosfets remain off until v fb d r ops to the 600 mv thresh old. becau se the mosfets a r e off, the l oad is sup p lie d by the o u tp ut cap a citor. if the inductor cur r ent does not reac h zero on any switching cycle, the controller immedi ately exits power-save and re tu rn s to forced continu ous mode. fig u re 6 sh ows powe r-sa ve opera t io n at l i ght load s. smart power-save protection active lo ads may l eak current fro m a hi gher vol t ag e into the sw itch er outpu t. und e r li ght lo a d con d ition s with po wer-save e nab led, th is ca n fo rce v out to sl owly rise an d re ach the o ver-voltage thresho l d, resul t in g i n a hard shut-down . sma r t p o wer-save pre v e n ts this co nditio n . wh en th e fb vol t a g e e xceeds 10 % abo ve n o minal , the device immed iately d i sabl es po wer-save, an d dl drives h i gh to turn on the lo w - si de mosf et . t h is d r aw s cu rre nt f r om v out through the inductor and cau s e s v out to fall. w hen v fb drops back to the 6 00 mv tri p poi nt, a n o rmal t on switching cycle begins . thi s me th od pre vents a ha rd ovp sh ut-d own a nd a lso cycles energy from v out back to v in . it also minimizes o pera t in g p o wer by avoid i ng fo rced co ndu ctio n mo de op e r at i o n . f i gu re 7 sh ow s typ i c a l w a ve fo rms f o r t h e sm ar t po wer save fe ature. figu re 4 - f o rced con t in uo us mo de o p erat ion fig u re 5 - ultraso nic po wer-save operatio n fb r ipple v oltage ( v fb ) ind u ctor c u rrent dc load c u rrent fb threshold (750 m v ) dh dl on-time (t o n ) dh on-time is triggered w hen v fb reaches the fb threshold dl dr i v es high w hen on-time is completed. dl remains high u ntil v fb falls to the fb threshold. fb ripple v oltage ( v fb ) ind u ctor c u rrent (0a) fb threshold (600 m v ) dh dl on-time (t o n ) dh on-time is tr iggered w hen v fb reaches the fb threshold after the 40 s time-o u t, dl dr i v es high if v fb has not reached the fb threshold. minim u m f s w ~ 25 khz 40 s time-o u t fig u re 6 - power-save mo de vishay siliconix sic401a, SIC401BCD document number: 63835 s12-2109-rev. c, 03-sep-12 www.vishay.com 17 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com smar tdrive tm for ea ch dh pulse , the dh driver i n itial l y turns o n the high side mosfet at a lo wer spe ed, all o win g a softer, smoo th turn-off o f the l o w-side dio de. on ce th e dio de is off and the lx voltag e has risen 0 . 5 v a bove p gn d , th e sma r tdrive circuit a u to mati cally d r ives the h i gh -si de mosfet on a t a rapi d rate. this techn i que reduc e s switching losses while main ta inin g high e f ficie n cy a nd al so a v oids the ne ed fo r snub bers fo r the po wer mosfets. curre nt limit prot ect ion the devi c e fea t u r e s p r ogrammabl e current limiting , whi c h is accompl i shed by u s ing th e r ds-o n of th e lo wer mosfet fo r curren t sensin g. the current limit is set by r il im resis t or. the r il im re sisto r conn ects fro m th e i li m pi n to the lxs pin which is also the d r ain of th e low-sid e mosfet. w hen the l o w-side mosfet is on , an interna l ~ 10 a current flows from the i li m pin an d throu gh th e r il im resistor, creating a voltage drop across the resi stor. wh ile the low-sid e mosfet i s o n , the in ductor current flows thr oug h it and cre a te s a voltage across th e r ds- o n . th e voltage acro ss the mosfet is ne gative wi th respect to grou nd. if thi s mosfet voltag e drop exceeds the voltage across r il im , the vol t a ge a t the i li m pin wil l be ne gative an d cu rrent l i mit w ill activate. the cu rre n t li mi t th en keep s the low - si de mosfet on and wi ll not a llo w an other hi gh-side on-time, un til th e curren t i n the l o w-side mosfet redu ces e nou gh to bring the i li m vo lta ge ba ck up to zero. this method regulate s the inductor valley curr ent at the leve l sh own by i lim in figur e 8. setting the vall ey current limit to 15 a resul t s in a pe ak in ductor current o f 15 a plu s p eak rippl e current. in th is situatio n, the ave r age (lo ad) current thro ugh the in ductor is 15 a plu s o ne-ha lf the pe ak-to - p eak ripp le current. the in te rn al 10 a current source is tempe r a t u r e compe n sated at 4100 p p m i n order to p r ovide tracking w i th the r ds- o n . the r il im value i s cal c u l ated by the fo llo wing eq uation . r il i m = 26 3 x i li m x [0.112 x (5 v - v dd ) + 1] w hen sel e cti ng a valu e fo r r il i m be sure not to exceed the ab solute maximum vol t a ge va lue for the i li m p in. no te that be cause the low-sid e mosfet wi th lo w r ds-o n is used for curren t sen s i ng, th e pcb l a yout, so lde r con nection s, and pcb con nection to the lx nod e must b e do ne care ful l y to ob ta in g ood re sults. r il im shou ld b e conn ected d i rectly to lxs (pin 28). sof t-start of pwm regulator sic4 01a/b has a prog ramma b le soft-start time th at is con t rol l ed by an external cap a citor a t th e ss pin . after the controller meets both uvlo and en/psv th resholds, the co nt ro lle r ha s a n i n te rn al cu rre nt s o u r ce of 3 a f l o w i n g throu gh the ss pin to charge th e cap a citor. durin g the start up pro c ess (figure 9), 5 0 % o f th e vo lta ge at the ss p i n is use d as th e reference for the fb comparator. th e pwm compa r ato r issue s an o n -time pu lse w hen th e vol t a ge a t the fb pi n i s less th an 40 % of the ss p in. as a re su lt, th e o u tput vol t ag e fo llow s the ss vo lta ge. the o u tput vo lta ge reach e s an d ma intain s re gula t i on whe n th e so ft sta r t voltage is ? 1.5 v. th e ti me b etw een the first lx pul se a nd v out rea c h i ng regu lation is the s o ft-start time (t ss ). the cal c u l ation fo r th e soft-start time is shown by th e foll owing eq uation . the vo lta ge a t the ss pin continu e s to ramp u p and eve n tuall y equ als 6 4 % o f v dd . aft e r t h e soft st art c o m p letes, the fb pi n vol t ag e is co mpared to an interna l reference of 0.6 v. th e de lay time be twe en the v ou t re gula t i on po int and p goo d goi ng hig h is sh own by th e fo llowi ng eq uation . fig u re 7 - smart po wer-save v out dr ifts u p to d u e to leakage c u rrent flo w ing into c out smar t po w er sa v e threshold ( 8 25 m v ) fb threshold dh and dl off high-side dr i v e (dh) lo w -side dr i v e (dl) n or mal v out r ipple v out discharges v ia ind u ctor and lo w -side mosfet single dh on-time p u lse after dl t u r n-off n ormal dl p u lse after dh on-time p u lse dl t u r ns on w hen smar t psa v e threshold is reached dl t u r ns off fb threshold is reached figu re 8 - valle y curren t lim i t i peak i lo ad i lim time ind u ctor c u rrent t ss = c ss x 1.5 v 3 a t pgood-delay = c ss x (0.64 x v dd - 1.5 v) 3 a www.vishay.com 18 document number: 63835 s12-2109-rev. c, 03-sep-12 vishay siliconix sic401a, SIC401BCD w ww.vishay.co m 18 document number: 63835 s12-2109-rev. c, 03-sep-12 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com pr e-bias start-up th e si c 4 01 a/b ca n st ar t up no rmally even whe n there is a n e x isti ng output vo lta ge presen t. t he soft start time is still th e sa me a s n o rma l sta r t up (whe n th e output voltage starts from ze ro ). th e o u tput vo lta ge sta r ts to ramp up whe n 40 % o f th e vo lta ge at ss pi n mee t s the exi s tin g fb vol t ag e l e vel. pre-b i as startup i s achi eved by turnin g off the l o wer gate w hen the in ductor current fa lls bel ow zero. th is me tho d p r events the o u tput vo ltage from d i schargi ng. po we r go od o u tp ut the p good (p ower goo d) o u tput i s an op en-dra i n output w h ich re quire s a p u ll-u p resistor. wh en the voltage at the fb p i n is 1 0 % bel ow the no minal vo ltage , p goo d is pu lled low. it i s h e ld l o w until the o u tput voltage re tu rn s a bove - 8 % of no mi n a l . p go od wil l tran sition lo w i f the v fb pin e x ce eds + 20 % of n o mina l, wh ich is a l so th e over-voltag e sh utdown thresh old. p go od also pull s low if the en/psv pi n is low w hen v dd is p r esent. output over-voltage prot ection ove r-vo l ta ge pr ot ect i on be co me s a c t i ve as so o n a s t h e d e vice i s e nab led. the thresho l d i s se t a t 6 00 mv + 2 0 % (7 20 mv). w hen v fb exceeds the ovp th resho l d, d l l a tches h i gh and the low - si de mosfet is tu rned on. d l re ma ins high and the controller remain s off, until the en/psv input is to gg l e d o r v dd is cycle d . th ere i s a 5 s de lay b u ilt in to th e ovp de te ctor to preve n t false tra n sitions. p go od is also low a f ter an ovp even t. ou tpu t und e r-v o ltag e protectio n w hen v fb fal l s 25 % be low its nomin al vol t a ge (falls to 4 50 mv) for eigh t consecu t ive clock cycl es, th e swi t che r is sh ut off an d the dh and dl drive s are pu lled low to tristate the mosfets. the controller stays off until en/psv is toggled or v dd is cycled. v dd uvlo , an d por u v lo (un der-voltag e lock-out) circu i try in hibi ts switchi n g a nd tri- states th e d h /dl d r i vers un ti l v dd rises above 3 v. an internal por (power-on reset) occurs when v dd e x ce eds 3 v, which resets the fault latc h and a soft-start counter cycle b egi ns wh ich prepa re s for soft-start. the si c401 a/b th en b egi ns a soft-start cycl e. the pwm will sh ut off if v dd fa lls be l o w 2. 4 v. ldo reg u l a to r si c401 a/b ha s an op ti on to bi as the switcher b y using an i n ternal ldo from v in . the ld o ou tp ut i s co nnected to v dd i n ternal ly. the o u tput of the ldo is programmab l e by usi n g e xte rn al resistors from the v dd pi n to a gnd (see figure 10 ). the feed back pin (fbl ) for th e ldo is regu lated to 750 mv. the l d o outpu t voltag e is set by th e fol l owi ng equ ation. a minimu m capa ci ta nce of 1 f re fe re nced to a gnd is n o rmall y req u ired at th e out put of the ld o fo r stabi lity. n o te th at if the ldo vo ltage i s set lowe r tha n 4.5 v, the mi nimum output capaci t an ce fo r the ldo is 1 0 f. ldo enl f u n c tion s the en l inp u t is used to e nabl e/disab l e the i n ternal ldo. w hen enl i s a lo gic low, the l d o is off. w hen enl i s ab ove the v in u v lo threshol d, the ldo i s en able d and the sw itch er is al so ena bled if th e en/psv a nd vdd are ab ove the i r thresh old . th e tab l e belo w su mma r i zes the function of en l a nd en/psv pi ns. the enl pin al so acts a s t he sw itch er u nder-vol ta ge lockout for t h e v in suppl y. whe n si c401 a/b is sel f -bi a sed fro m the ld o an d ru n s fr om the v in powe r so urce onl y, th e v in uvl o fi gure 9 - soft-start t i min g diag ram figu r e 1 0 - l do ou tpu t vo ltag e selectio n en/psv enl l do switc h er disab l ed lo w , < 0.4 v o ff off enab le d l o w , < 0.4 v o ff on disab l ed 1 v < high < 2.6 v o n o ff enab le d 1 v < high < 2.6 v o n o ff disab l ed high , > 2 . 6 v o n o ff enab le d h igh , > 2 . 6 v o n o n v ldo = 750 mv x 1 + r ldo1 r ldo2 vishay siliconix sic401a, SIC401BCD document number: 63835 s12-2109-rev. c, 03-sep-12 www.vishay.com 19 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com feature can be u s ed to p r event f a lse uv faults for t h e p w m ou tp ut by p r ogramming wi th a re sisto r di vi der at the v in , enl an d a gn d pi ns. whe n sic4 01a/b has a n externa l bia s voltag e at v dd and the enl pin is used to prog ra m the v in uvlo fea t u r e , th e vo ltage at fbl n eed s to b e h i gh er than 75 0 mv to force the ldo off. timing is impo rtan t wh en drivi ng enl with lo gic and n o t impl ementing v in uvl o . the enl pin must tra n sition from high to low within 2 switching cycles to avoid the pwm output turnin g off. if en l goe s belo w th e v in uvlo th re shol d and stays ab ove 1 v, then th e swi t ch e r wil l turn off but the ldo wil l re main on . ldo start-up before star t-up, the ldo che cks the status of the following sign als to e n sure prop er opera t io n can be main ta ined . 1 . en l pi n 2. v ld o ou tp ut wh en the enl pin i s h i gh an d vin is ab ove th e uvlo p o int, the l d o will beg in start-up. duri ng the ini t i a l p hase, wh en the v dd voltag e (whi ch is the ld o o u tp ut voltage ) is less than 0.75 v, the ld o ini t i a te s a curren t -l imite d start-up (typical ly 65 ma) to charg e th e o u tput ca pacitors whil e protecting from a sh ort circuit eve n t. w hen v dd is g r eater than 0.75 v but still le ss tha n 90 % o f i t s fin a l val ue (a s sensed at the fbl p i n), the ld o curren t l i mit i s increa se d to ~1 15 ma. whe n v dd ha s rea c hed 9 0 % of the fina l valu e (as se nsed at the fbl pi n), the l d o curren t li mi t is in cre a sed to ~ 2 00 ma and the ldo outpu t is qu ickly driven to the n o minal va lue b y the in tern al ldo regul ator. it is recommend ed that durin g ldo start-u p to h o ld the pw m switchin g o f f un ti l the ldo ha s reach ed 9 0 % of the fin a l va l ue. this preven ts o v erloa d ing the current-limited l d o ou tp u t du ri ng the ldo start-up. due to th e in iti a l cu rre n t limitation s o n the l do d u ring powe r up (figure 11 ), any e x te rn al loa d a t tache d to th e v dd pin must be l imited to less th an the sta r t up cu rre n t b e fo re th e ldo ha s rea c h ed 90 % of its final re gula t i on valu e. ldo switch-ove r poer ation the si c401 a/b i n cludes a switch-over fun ctio n for the ldo. the switch-over function i s de signe d to i n crease e f ficie n cy by usin g th e more effi cient dc/dc conve r ter to powe r the ldo output, a v o i di ng th e less effici ent l d o regu lator when pos sible. the switch- o ver func ti on con n e c t s t h e v dd pin dir e ct ly to the v out pin usin g a n interna l swi t ch. whe n the switch-over i s co mplete the ldo is tu rned o f f, which re sults in a po wer saving s and ma ximi zes efficienc y. if the ldo ou tp ut is use d to bi as the si c401a / b, then after switch- o ver the de vi ce i s sel f -po w ered from the swi t chi ng regul ator w i th the ldo tu rn ed off. the switch-over starts 32 switching cycles after p good ou tp ut goe s high . the voltag es at the v dd a nd v out pi n s ar e then compa r e d ; if the two vo lta ges are w i th in 300 mv of ea ch other, the v dd p i n conn ects to the v out pin u sing an in te rn al swi t ch, an d the l do i s turn ed off. to a v o id u n want ed switch-ove r, th e mi nimum di fference be tw een the voltag es for v out an d v dd sho u ld be 5 00 mv. it is no t re co mme nded to use th e switch-ove r fe ature for an ou tp ut voltage less than v dd uvlo th re shold since the sic4 01a/b i s n o t op eration a l bel ow that thresho ld. switch-over mosfet paras i tic diodes the switch-over mosfet contai ns p a rasitic dio des th at a r e in heren t to its co nstru ctio n , as sho w n i n figure 12. if the vol t ag e at the v out pin is hig her than v dd , then t h e respe cti ve dio de wi ll turn o n an d the curren t w ill flo w th rough this dio de. this ha s the poten tial of da ma ging the d e vice. therefore, v out must be less than v dd to preven t da ma ging the de vi ce. desi gn procedure w hen de signi ng a switch mo de supp ly the i npu t voltage ran ge, lo ad cu rre n t, sw itch ing freq uen cy, a nd i ndu ctor ri pple curren t must be sp ecified. the ma xi mum inp u t voltag e (v in ma x. ) i s the h i gh est specified in put vo ltage. the min i mum i nput vo ltage (v in min . ) is de te rmi ned by the lo west i nput voltag e after eva l uatin g the vol t ag e drops due to conn ecto rs, fu se s, switches, a nd pcb traces. the follo wing p a rameters d e fine the de si gn: ? nomin a l outpu t voltag e (v out ) ? sta t i c or dc outpu t tolera nce ? tra n sien t respon se ? maximum load current (i out ) there are two va lues of l oad curren t to evaluate - co nti nuous lo ad cu rrent an d p eak l oad current. co nti nuo us lo ad current rel a te s to thermal stresses w h ich d r ive the se lection of the in ductor and in put capaci t o r s. peak loa d current de te rmi nes instantan eous compo nent stre sses a nd filtering requ iremen ts su ch as i nducto r satura tio n , outpu t ca pacitors, an d design of the curren t limit circuit. the follo wing val ues are used in thi s de sign: ? v in = 12 v 1 0 % fig u re 11 - ldo start-up figure 12 - switch -ove r mosfet parasitic d iod es v out ldo p ar astic diode s w itcho v er mosfet s w itcho v er control v dd www.vishay.com 20 document number: 63835 s12-2109-rev. c, 03-sep-12 vishay siliconix sic401a, SIC401BCD w ww.vishay.co m 20 document number: 63835 s12-2109-rev. c, 03-sep-12 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com ? v ou t = 1.5 v 4 % ? f sw = 3 00 khz ? lo ad = 15 a max. frequen c y s e l e cti o n se lection of th e swi t chi ng freq uency re quire s making a trade -off betwee n the size and cost of the external filter co mp onen ts (i ndu ctor and outpu t ca pacitor) a nd th e po wer conversion efficiency. the desire d switchin g frequ ency is 300 khz which results from using comp onen t sele cte d for optimum size and co st. a resistor (r ton ) i s u s ed to progra m the on -time (in d irectly se tting the frequ ency) u s ing the follo wing e quatio n. to select r ton , use th e ma ximum val ue fo r v in , an d for t on u s e the va lue associ ate d with ma ximum v in . su bsti tu tin g fo r r to n resul t s in the fo llow i ng sol u ti on. r ton = 1 33.3 k ? , use r to n = 13 0 k ? . ind u cto r select ion in order to de te rmin e the in duc ta n ce, t h e ri pp l e cu rre n t mu st first b e define d . l o w ind u ctor va lues resul t in smal ler size but crea te hi gher rippl e curren t which can reduce efficien cy. h i ghe r ind u cto r valu es wil l red u ce the rippl e curre nt/vol tag e a nd fo r a gi ven dc resistance are more efficien t. h o wever, l a rger in ductance transla te s d i re ctly i n to large r p a ckage s an d h i ghe r cost. co st, size, outpu t ri pple , a nd e f ficie n cy are a l l u sed in the sele ctio n process. the ripp le current will al so se t th e boun dary fo r p sav e o peratio n. the switchin g wi ll typ i call y en ter p sa ve mode w hen the loa d curren t decrea s e s to 1/2 o f the rippl e curren t . for exa m p l e, if ripp le curren t i s 4 a then p save opera t io n wi ll typica lly start for lo ads le ss tha n 2 a. if ripp le curren t is set at 4 0 % of maximum l oad cu rre n t, the n p sa ve will sta r t for lo ads le ss th an 20 % o f maximum current. the in ductor value i s typica lly selected to provid e a rippl e cu rre n t th at i s betwee n 25 % to 50 % of the maximum loa d cur r en t. t h i s pr ovi d e s a n op ti ma l trad e-off betwe en cost, e f ficie n cy, an d tran sient performance. d u ring the on-time, vo ltage across th e i ndu ctor is (v in - v out ). th e eq u a t i on f o r de te rmi n i ng i n du ct an ce i s sh own next. example in this e xample, the i nductor rip p le cu rre n t is set equ al to 3 0 % of the ma ximum lo ad cu rre n t. th us ripp le current wi ll b e 3 0 % x 15 a or 4.5 a. to fin d the min i mum ind u cta n ce n eed ed, use the v in and t on valu es that correspo nd to v in max . a sl igh t ly l a rger va lue of 1 h is sel e cted. th is wil l de crea se t h e m a xi mu m i ripple to 4.43 a. n o te that th e in ductor must be rated for the maximum dc l oad curren t pl us 1 / 2 o f the rippl e current. the ripple c u rr ent under minimum v in con d ition s is a l so ch ecked usin g th e fol lowi ng equ ations. c a pa citor selection the o u tput ca pacitors are cho sen ba se d upo n requi red esr a nd cap a citance. the maximum esr requ irement is co ntro lle d by the o u tput ri pp le re quire me nt and the dc tol e rance . the ou tpu t vol t a ge ha s a d c va lue tha t is eq ual to the vall ey of the o u tput ripp le p l us 1/2 o f th e pe ak-to - p eak ri pple . a ch ange in the o u tput ripp le vol t ag e wil l le ad to a cha nge in d c vo ltage at th e o u tput. the de si gn goal for o u tput vol t ag e ri pple is 3 % of 1.5 v or 4 5 mv. th e ma ximum esr val ue all o wed i s sh own by the fol l owi ng equ ations. th e ou t p u t ca pa ci ta n ce is u sua lly chose n to meet tran sient re quire me nts. a worst-case l oad rele ase, from maximum l oad to no loa d at the exact mo me nt wh en ind u ctor curren t is a t th e peak, d e termines th e re quire d cap a citance . if the lo ad re lease is i n sta n tane ous (lo ad ch ang es from maximum to zero in < 1 s ), the output capacitor must absorb all the i ndu ctor's sto r ed en ergy. th is will cause a pea k vo ltage on the ca pacitor accordi ng to the foll owin g equa ti on. assumi ng a p eak vol t a ge v peak of 1.65 v (15 0 mv rise up on l oad rele ase), and a 15 a load rele ase, the requi red ca pacitan ce i s sho w n by th e n e xt e quatio n. r ton = 25 pf x f s w k t o n = v out v i n max. x f s w l = ( v i n - v out ) x t o n i ripple l = (13.2 - 1.5) x 379 ns 4.5 a = 0.99 h t o n _ v i n min. = 25 pf x r to n x v out v i n min. i ripple = ( v i n - v out ) x t o n l i ripple_ v i n min. = (10. 8 - 1.5) x 451 ns 1 h = 4.19 a = 451 ns esr max. = v ripple i ripplemax. esr max. = 10.2 m = 45 m v 4.43 a c out_min. = l (i out + x i ripplemax. ) 2 ( v peak ) 2 - ( v out ) 2 1 2 vishay siliconix sic401a, SIC401BCD document number: 63835 s12-2109-rev. c, 03-sep-12 www.vishay.com 21 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com duri ng the lo ad rele ase time, the vo lta ge cross th e ind u cto r is a pproxi m a t e l y - v ou t . thi s causes a do wn-slop e or fal ling di /dt in the ind u cto r . if th e load d i /dt i s no t much faste r than the di/dt o f the in ductor, the n the ind u ctor current will ten d to track th e falli ng lo ad cu rre n t. this wi ll red u ce the e xcess in ductive energ y th at must be ab sorbed by th e o u tp ut capa citor; therefore a small e r ca pacitance ca n b e used. the fol l owi ng ca n b e u s ed to calcul ate the ne eded capa citance for a g i ven di lo ad /dt. peak in ductor cu rre n t i s sho w n by the n e xt eq uation . i lp k = i max. + 1/2 x i ri ppl e m a x . i lp k = 10 + 1/2 x 4.4 3 = 12.21 5 a i max. = ma xim u m loa d re lease = 15 a exam ple this w ould cau se the ou tp ut curren t to move from 15 a to 0 a in 4 s, g i ving the min i mum o u tp ut ca pacitance requ iremen t shown i n the fol lowi ng equ ation. note that c out is much small e r in this exa m p l e, 169 f compa r e d to 316 f ba sed on a w o rst case l oad rel ease. to meet the tw o de sign cri t e r ia o f mi nimum 3 16 f and maximum 10.2 m ? esr, sele ct one ca pacitor of 3 30 f and 9 m ? esr. stability co nsider ations unstab le o peratio n is p o ssibl e wi th ada ptive o n -ti m e control l ers, a nd usua lly ta kes th e form of doub le-pu l sing o r esr loop i n sta b il ity. dou b le -p ulsin g occurs due to switching n o ise see n at the fb in put or becau se the fb ri pple vo ltag e is to o lo w. th is cau s e s the fb compa r a t o r to tri gge r pre m a t u r e l y after the 250 n s mini mu m o f f-time has e xpired . in extreme case s the noise can cause th re e o r more successi ve on -times. do uble - pu lsing wil l resu lt in higher rip p le voltag e a t the ou tp ut, but in most app licatio ns it wil l no t a f fect ope rati on. this form of in stab ili ty can usua lly b e avo ided by p r ovidi ng the fb p in w ith a smoo th, clea n ripp le sign al t hat is at least 10 mvp-p, whi c h may dictate th e n eed to increa se the esr of the o u tput cap a citors. it i s also impe rative to provid e a prop er pcb la yout a s d iscussed in the la yo ut guid elin es se cti on. ano t h e r w a y to el iminate do ubli ng-pu lsing i s to add a smal l (~ 10 p f ) capa ci to r a c ro ss the up per fe edba ck resi stor, as sho wn in figu re 13. th is ca pacitor sho u ld b e left u npop ula t ed un ti l it ca n be con f irmed tha t do ubl e-pul si ng exi s ts. ad ding the c top capa cito r will coupl e more rip p le into fb to help el imina t e the probl em. an o p tiona l conn ecti on on th e pcb sh ou l d b e av ai l a b l e fo r th is ca pa ci to r. esr lo op i n stabil i ty is caused by in suffici ent esr. the de ta ils o f th is stabi lity issue are discusse d i n the esr re quire me nts se ctio n. the b e st me tho d for checking stabil i ty is to app ly a zero -to-ful l l oad transi ent a nd ob se rve the output vol t ag e rip p le env el ope fo r overshoo t and ri ngi ng. ringing for more than one cycle after the initial step is an in dicatio n tha t the esr sh oul d b e increa se d. esr requirem ents a min i mum esr is req u ired for two reason s. on e rea son is to g ene rate en oug h o u tput rip p le voltag e to provide 10 mvp-p a t the fb p i n (afte r the re si sto r d i vider) to avoid do ubl e-pul si ng. the secon d re ason is to p r e vent instabil i ty du e to in suffici ent esr. the on -time control reg u la tes th e va lle y of the o utput rip p le vo lta ge. this ripp le vol t a ge is the su m of the two vol t ag es. on e i s th e ri pple ge nerated by the esr, th e o t h e r is the rip p le d ue to capa citi ve chargi ng an d discha r ging during the switching cycle. for most applic ations the mini mu m esr ripp le voltag e is d o mina te d by the o u tput capacitors, typic a lly sp or poscap devices. for stability the esr zero of the ou tp ut ca pac itor shou ld be lowe r than ap proximatel y on e-third t he switchin g freq uen cy. the formula fo r mi nimum esr is sh own b y th e foll owing eq uation . c out_min. = 1 h (10 + x 4.43) 2 (1.65) 2 - (1.5) 2 c out_min. = 316 f 1 2 rate of change of load c u rrent = di load dt c out = i lpk x l x - x dt 2 ( v pk - v out ) i lpk v out i max. dl load dl lo ad dt = 2.5 a 1 s c out = 12.215 x 1 h x - x 1 s 2 (1.65 - 1.5) 12.215 1.5 10 2.5 c out = 169 f fi gu re 13 - ca pacit o r co upli ng t o f b pin v out r 1 r 2 t o fb pin c to p esr min. = 3 2 x x c out x f s w www.vishay.com 22 document number: 63835 s12-2109-rev. c, 03-sep-12 vishay siliconix sic401a, SIC401BCD w ww.vishay.co m 22 document number: 63835 s12-2109-rev. c, 03-sep-12 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com u s ing ce ramic output c a pa citors when the system is using hi gh esr value capac i tor s , the fee dback vol t a ge rip p le l ags the p hase node voltage by 90. there f o r e , th e co nverter is easil y sta bili zed. w hen th e system is using ceramic output capacitors, the esr v a lue is n o rmally to o small to mee t th e a bove esr criteria . as a re su lt, th e fee dback vo ltage ripp le is 18 0 from the ph ase n ode an d b eha ve s in an u n sta b le mann er. in thi s ap plica t io n i t i s necessa ry to add a small vi rtu a l esr n e twork that is co mp osed of tw o cap a citors and on e resistor, as sh own i n figure 14. the rippl e vol t ag e at fb is a superp o sition of tw o vol t ag e sources: the voltage across c l an d ou tp ut ripp le vo ltage. they are de fi ned in the foll owin g e qua ti ons. figu re 15 show s the mag n itude o f the rip p le con t rib u tion du e to c l a t the fb pin . it i s sho w n by the fol l owin g equ ati on. fi gu re 1 6 sh ow s th e ma gn i t u d e o f th e ri pp l e co nt ri bu ti o n du e to the outpu t voltag e ri ppl e a t the fb pi n. it i s sho w n by th e fol l owi ng equ ation. the pu rpose of thi s ne twor k is to coup le the indu ctor current ri pple in fo rmatio n i n to the fe edba ck voltage such th at the fee dba ck vol t ag e has 90 p hase la g to the swi t chi ng no de si mi lar to the case o f u s i ng stan dard h i gh esr capa cito rs. thi s is ill ustra t e d in fi gure 17 . the ma gni tud e of the feed ba ck rip p le vo ltage, wh ich is d o mina te d by th e con t rib u tion fro m c l , i s controll ed b y the va lue o f r 1 , r 2 an d c c . if the corne r freq uency of (r 1 //r 2 ) x c c i s too high , th e rip ple magni tu de at th e fb pi n wi ll be smal ler, wh ich can le ad to doub le-pu l sing . conve r se ly, if the co rner frequ ency of (r 1 // r 2 ) x c c is too low , the ripp le ma gnitud e at fb pi n wil l be hi gher. sin ce the si c401 a/b reg u l at es to th e va l l e y of t h e ri pp l e vo l t a g e a t t h e fb p i n , a h i gh ripp le ma gnitud e is und esirabl e a s it sign ificantly i m pacts the outpu t voltage reg u latio n . as a resu lt, it is d e sirab l e to select a corner fre que ncy for (r 1 // r 2 ) x c c to a chieve e noug h, bu t no t excessive, ri pple mag n itude a n d p hase ma rgin. the co mp one nt va lue s fo r r 1 , r 2 , and c c sh ould b e calcul ate d using the foll owin g procedu re. select c l (typi c a l 10 nf) an d r l to match with l a nd dcr time con s tan t usin g th e fol l owi ng equ ation. figure 14 - virtual esr ra mp c u rrent f i gu re 15 - f b voltage b y c l vo ltag e v cl = i l x dcr (s x l/dcr + 1) s x r l x c l + 1 v out = i l 8 c x f s w v fb cl = v cl x (r 1 //r 2 ) x s x c c (r 1 //r 2 ) x s x c c + 1 fig u re 16 - fb vo ltag e by ou tput voltage figure 17 - fb v o ltag e in ph asor di agram v fb v out = v out x r 2 r 1 // + r 2 s x c c 1 vishay siliconix sic401a, SIC401BCD document number: 63835 s12-2109-rev. c, 03-sep-12 www.vishay.com 23 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com select c c b y usin g th e fol l owi ng equ ation . the resistor values (r 1 and r 2 ) in the voltag e divid e r ci rcu i t set the v ou t for the switcher. the typical value for c c is from 10 p f to 1 nf . drop out perf orman c e the outpu t voltag e adju s tmen t rang e fo r con t i nuou s cond uction op eration is limited by th e fixed 2 50 ns (typica l ) mini mu m off-time o f the one -shot. whe n wo rki ng w i th lo w in put vol t ag es, the duty-factor l i mit must be calcu l ated using worst-case values for on and off tim e s. the duty-fa cto r li mi ta tio n is sh own by th e next e qua tio n . the ind u ctor re si sta n ce and mo sfet o n -sta te vo lta ge drop s must be inclu ded whe n pe rfo r min g wo rst-case dropo ut du ty-facto r cal c ulatio ns. syste m d c a ccurac y (v ou t controller) three factors affect v out accuracy: the trip poi nt of th e fb error comp arator, the rippl e vol t ag e varia t i on wi th line and lo ad, and the e x tern al resistor tolera nce. the e r ro r co mp ar at or o ffse t i s t r im me d so th a t un d e r sta ti c co nd i ti o ns it trips wh en th e fe edba ck pi n is 6 00 mv, 1 %. the on -time pu lse from the si c401 a/b in the d e sign examp le is ca lcula t e d to gi ve a pse udo-fixed fre quency of 30 0 kh z. some fre que ncy va ri ation wi th l i ne an d load is expe cte d . this va riation chan ges th e o u tput rip p le vol t ag e. becau se ada ptive on -time co nverters re gul ate to th e valle y of the o u tput ri pple, ? of t he outpu t ripp le app ears as a d c regu lation e r ro r. fo r exampl e, if th e o u tput ri pple is 50 mv with vin = 6 v, then th e mea sured dc ou tp ut wil l be 25 mv ab ove th e co mparator trip p o in t. if th e ripp le in crea ses to 80 mv with v in = 17 v, the n the measu r e d dc ou tp ut will b e 40 mv ab ove the compa r ator trip. the best way to m i nimize t h is effect is to minimize the ou tp ut rip p le. the u se o f 1 % fee dba ck resistors may resu lt in up to 1 % error. if tigh te r dc accura cy is re qui re d, 0 . 1 % resistors shou ld be used . the output i ndu ctor value may ch ang e wi th curren t . this will chan ge the o u tp ut ri pple and the r e f o r e will h a ve a mino r effect on the dc ou tp ut voltage . the outpu t esr a l so a f fects the outpu t ripp le and thu s ha s a mino r e f fect o n the d c ou tp ut vol t ag e. switching freque ncy va riation the swi t chi ng frequ ency varie s w i th loa d current as a re sult of the powe r losses i n the mosfets and dcr o f the in ductor. for a conven ti onal pwm constant-freque ncy conv e r te r, as l oad i n crease s the duty cycl e al so increa ses sli ghtly to compen sate for ir and swi t ch ing l o sses in the mosfets and ind u cto r . an ad aptive on-time co nverter must also compens a te for the sam e losses by inc r easing the effective duty cycle (more time is spent draw ing ener g y from v in as losses incr ease). the on -ti m e is essen t i a lly co nstant for a g i ven v out /v in co mbina t i on, to offse t the l o sses the o f f- time will tend to re duce slig htly a s lo ad increa ses. th e net effect is th at switchin g fr eq uency increa se s sli ghtly w ith in cre a sing load . r l = l dcr x c l c c 1 r 1 //r 2 3 2 x x f s w x duty = t o n (min.) t o n (min.) x t off(max.) www.vishay.com 24 document number: 63835 s12-2109-rev. c, 03-sep-12 vishay siliconix sic401a, SIC401BCD w ww.vishay.co m 24 document number: 63835 s12-2109-rev. c, 03-sep-12 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com s i c401 (2) (3) evaluation ref board evaluation board schematic ton lx bs t soft lx vdd vo bst pgd ilim vin fbl en _psv vout fb vdd c27 1uf c27 1uf p7 pgood p7 pgood 1 c30 68pf c30 68pf + c18 330uf + c18 330f + c12 150uf + c12 150uf c26 1uf c26 1uf r39 0r r39 0r c25 68pf c25 68pf r14 0 r14 0 r10 r10 5.11k m3 m3 1 1 b3 vo b3 vo 1 r23 5.11k r23 c11 0.1uf c11 0.1uf r52 0 r52 0 c29 3.3nf c29 3.3nf + c22 68uf + c22 68uf p6 enl p6 enl 1 l1 1.5 h r8 4.64k m2 m2 1 1 + c20 68uf + c20 68uf c15 10f c15 p11 vo_gnd p11 vo_gnd 1 m1 m1 1 1 r15 10k r15 10k r7 0r r7 0r r30 130k r30 130k p1 vdd p1 vdd 1 p8 vin p8 vin 1 p9 vin_gnd p9 vin_gnd 1 c28 0.1uf c28 0.1uf p10 vout p10 vout 1 r13 100 r13 100 c13 0.01uf c13 0.01uf + c16 330uf + c16 330f c6 1uf c6 1uf b4 vo_gnd b4 vo_gnd 1 p2 en_psv p2 en_psv 1 b2 vin_gnd b2 vin_gnd 1 m4 m4 1 1 + c10 68uf + c10 68uf b1 vin b1 vin 1 u1 u1 sic403 fb 1 fbl 5 vdd 3 agnd 30 vout 2 vin 6 soft 7 bst 8 vin 9 vin 10 vin 11 nc 14 lx 23 nc 12 pgnd 22 pgnd 21 lx 25 lx 24 pgnd 20 pgnd 19 pgnd 18 pgnd 17 pgnd 16 pgnd 15 enl 32 ton 31 agnd 35 en/psv 29 lxbst 13 ilim 27 pgd 26 lxs 28 lx 33 vin 34 agnd 4 vishay siliconix sic401a, SIC401BCD document number: 63835 s12-2109-rev. c, 03-sep-12 www.vishay.com 25 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com bill o f m a te ria l s qty . r e f . desig n ator pc b fo otp r int v alu e v o lta g e desc r i p t io n p ar t nu mb er manufac turer 3 c 6, c11, c 1 4 s m0603 0.1 f 50 v c ap , 0.1 f , 50 v , 0603 gener ic component 3 c 10, c20, c 22 593d 68 f 20 v 68 f t a n, 20 v , 593d , 20 % 593d68 6x0020d2t e3 1 c 12 rad i al 150 f 35 v c ap , radial, 150 f , 35 v e u-f m 1v151 1 c 13 sm0402 0 . 01 f 50 v c ap , 0.01 f , 50 v , 0402 gener ic component 1 c 21 sm1206 10 f 16 v 10 f , 16 v . x7r. b , 1206 gener ic component 3 c 16, c17, c 18 s m593d 330 f 6.3 v 330 f , 6.3 v , d 593d337x06 r3e2 2 c 25, c30 s m0402 68 pf 50 v c ap , 68 p f , 50 v , 0402 gener ic component 2 c26, c27 s m0805 1 f 10 v 4 .7 f , 10 v , 0805 gener ic component 1 c 28 sm0402 0.1 f 10 v c ap , 0.1 f , 10 v , 0402 gener ic component 1 c15 sm1210 2.2 f 35 v cap , 2.2 f , 35 v , 1210 gmk 3 2 5 bj225m n 1 c29 sm0603 3.3 nf 25 v c a p , c e r, 22 nf , 25 v g ener ic component 1 l1 i hlp4040 1 h 0 1 h ihlp4040d zer1r0 m01 4 m 1, m2, m3, m4 0 0 0 n ylonon stand off 8834 8 p1, p2, p6, p7, p8, p9, p10 , p11 t e r m inal 0 0 t e st p o ints 1573-3 1 r 7 s m0603 0 ? 50 v r es , 0 ? gener ic component 1 r 8 s m0603 3.92k 50 v r es , 12.4k, 0603 gener ic component 1 r 10 sm0603 5.11k 50 v r es , 5.11k, 0603 gener ic component 1 r 13 sm0402 100 ? 50 v 100 r, 5 0 v , 0402 gener ic component 1 r 14 sm0402 0 ? 50 v 100 r, 5 0 v , 0402 gener ic component 1 r15 sm0603 10 k 50 v res , 10k, 50 v , 060 3 g ener ic component 1 r 23 sm0603 7.15k 50 v r es , 5.11k, 0603 gener ic component 1 r 30 sm0603 13 0k 50 v r es , 69.8k, 0603 gener ic component 1 r 39 sm0402 0 ? 50 v 0 r, 50 v , 0402 gener ic component 1 r 52 sm0603 0 ? 50 v r es , 31.6k, 5 0 v , 0603 gener ic component 1u 1 po w e r p a k mlp55-32l 00 15a micro b u ck inte g r ate d buc k regulator with prog r a mmab l e ldo sic401a cd-t1-ge3/ sic 401bcd-t1ge3 4 b 1, b2, b3, b4 0 0 0 banana j a ck 575-4 www.vishay.com 26 document number: 63835 s12-2109-rev. c, 03-sep-12 vishay siliconix sic401a, SIC401BCD w ww.vishay.co m 26 document number: 63835 s12-2109-rev. c, 03-sep-12 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: powerictechsupport@vishay.com p a c k ag e dime ns io n s no t e : 1. use millimeters as the primary m easurement. 2. dimen s ioning and toleran c es conform to a s me y1 4.5 m - 1994. 3. n is the nu mber of te rminals nd is the n umber of t erminals in x-directio n and ne is the n u mber of t e rminals in y-directio n. 4. dimen s ions applies to plated terminal and is m easured betw een 0.20 mm a nd 0.25 mm from terminal tip . 5. the pin #1 iden tifier mu st b e exis ted on the top sur f ace of the pac kage by u s ing inde nt at ion mar k or oth e r fea t ur e of pa ckage b od y . 6. e x act shape and size of t h is feature is optional. 7. p a ckage warpage max. 0.08 mm . 8. a p plied only for terminals. vishay s iliconix ma int a ins wor l dwide manuf act u ring capab ilit y . pr oduct s may be manuf act u red at one of s e v e ral quali f ie d locat i o n s . reli ability da ta for sili c o n t e c h nolo g y an d package reli abilit y repre s e n t a compo s it e of all qua lifi ed locat i ons. for r e lat ed do c u me nt s such as p a ck a ge/ ta pe drawin gs, pa rt markin g, an d relia bility da ta , see ww w. vishay. c o m / p p g?63 835 . t op view side view bottom view dim. mi llimet er s in c hes no te min. nom. max. mi n. nom. max. a 0.70 0.75 0.80 0.027 0.029 0.03 1 a1 0.00 - 0 .05 0 .00 - 0.00 2 8 a2 0.20 ref . 0.0 08 ref . b 0.20 0.25 0.30 0.078 0.098 0.11 0 4 d 5 . 00 bsc 0.196 bsc e 0 . 50 bsc 0.019 bsc e 5 . 00 bsc 0.196 bsc l 0.35 0.40 0.45 0.013 0.015 0.01 7 n3 2 3 2 3 nd 8 8 3 ne 8 8 3 dim. millime t er s i n c hes min. no m. max. m i n. no m. max. d2-1 3.43 3.48 3.53 0.135 0.137 0.139 d2-2 1.00 1.05 1.10 0.039 0.041 0.043 d2-3 1.00 1.05 1.10 0.039 0.041 0.043 d2-4 1.92 1.97 2.02 0.075 0.077 0.079 d2-5 0.36 0.014 e2-1 3.43 3.48 3.53 0.135 0.137 0.139 e2-2 1.61 1.66 1.71 0.063 0.065 0.067 e2-3 1.43 1.48 1.53 0.056 0.058 0.060 e2-4 0.45 0.018 document n u mber : 64 714 www .vish a y . com re vision: 29-dec-08 1 package information vishay siliconix po we r p ak ? mlp55 - 32l case outline no tes 1. use millime t ers as the primary measureme n t. 2. dimension i ng an d tolerances conform to asme y14.5m. - 1994. 3. n is the number of terminals. nd is the number of terminals in x-direction and ne is the n umber of t erminals in y-directio n. 4. dimension b applies to plated terminal and is m easured bet ween 0.20 mm and 0.25 mm from terminal tip . 5. t he pin #1 ide n tifier mu st be exist ed on the top surface of the package by using i ndentation mark or other feature of package body. 6. exact shape a nd size of this fe ature is optio nal. 7. packag e warpa ge max. 0.08 mm. 8. applied only for terminals. b y marking e pin 1 dot top v ie w d (5 mm x 5 mm) 32l t/slp e2 - 2 ( n d-1) xe ref. bottom v ie w side v ie w d2 - 1 r0.200 pin #1 identification b e d2 - 4 d2 - 3 e2 - 3 d4 9 24 25 32 a 0.10 c b 2x 0.0 8 c c a a2 a1 b ( n d-1) xe ref. l 0.36 0.360 5 6 0.10 c a b 4 d2 - 2 e2 - 1 0.10 c a 2x 8 17 16 0.45 1 mil l imet e r s i n ches dim m in . n om. m a x . m in. n om. m ax. a 0 .80 0.85 0.90 0.031 0.033 0. 035 a1 (8) 0 . 00 - 0.05 0.000 - 0. 002 a2 0.20 ref. 0.008 ref . b (4 ) 0 . 20 0.25 0.30 0.078 0.098 0. 011 d 5 .0 0 bs c 0 .196 bsc e 0 .5 0 bs c 0 .019 bsc e 5 .0 0 bs c 0 .196 bsc l 0 .35 0.40 0.45 0.013 0.015 0. 017 n (3 ) 32 32 nd (3 ) 88 ne (3 ) 88 d2 - 1 3 .43 3 .48 3 .53 0 .135 0.137 0. 139 d2 - 2 1 .00 1 .05 1 .10 0 .039 0.041 0. 043 d2 - 3 1 .00 1 .05 1 .10 0 .039 0.041 0. 043 d2 - 4 1 .92 1 .97 2 .02 0 .075 0.077 0. 079 e2 - 1 3 .43 3 .48 3 .53 0 .135 0.137 0. 139 e2 - 2 1 .61 1 .66 1 .71 0 .063 0.065 0. 067 e2 - 3 1 .43 1 .48 1 .53 0 .056 0.058 0. 060 ecn: t - 08957 -rev. a, 29-dec-08 dwg: 5983 legal d i sclaim er notice www.vishay.com vishay revision : 02-oct- 12 1 d o cu ment number: 91000 disclaimer all pro d uct, produ c t specificatio n s and data are s u bject to change with o u t notice to impro v e reliabil ity , function or design or otherwise. v i sha y in te rtec h n ology, i n c . , its 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for ce rtai n type s of applications are b a sed on vi shay s kn owle dge of typic a l require m e n ts tha t are ofte n plac ed on vish ay produc t s i n gene ric appli cat ions. suc h st ate m ents are n o t bin d ing state m ent s about t h e sui t abil ity of products f o r a particular applicati o n . it is th e cu stomers respon sib ilit y t o validate th at a particu lar pr oduct with the properties descr i bed in th e product speci f ication is suitable f o r use in a par t icular ap plication. par a meters pr ovid ed in datasheets and/or specification s may v a ry in different ap plications an d performance m a y vary over time. all op erating par a meters, including typical pa r a meters, m u s t be v a lidated for each cu stomer a p pl ica tion by the cu stomer s techni cal experts. produ c t specif ications do not expa nd or othe rwise modi fy vi sh ay s terms an d condit ions of purchase, including but not limited to th e wa rra nty exp r ess e d th e r ein . except as expressly indicate d i n w r iti n g, v ishay produ cts are not design ed for u s e i n me dica l, li fe- savin g, or li fe- sustai n ing applications or for any other application in which the failu re of the vi sh ay product coul d result in person al inju ry or deat h. customers us i n g or sell ing vishay p r oducts not express ly indicated for use in such applications do so at thei r own ri sk. ple a s e cont act au thorize d vish ay personn e l to ob tain written terms and conditions regarding products designed for s u ch applications. no license, express or impl ied, by estoppel or otherwise, to an y i n tellectu a l prope rty rights is granted by this docum e nt or by any con d u c t of v ishay. produc t name s and markings noted herein may b e trad emarks of thei r re spe c ti ve owne rs. material category policy vishay intertech nology, inc. hereby certi fies that all its products that are id en tified as rohs-compliant fulfill th e defi nit i ons and rest ri ct ions defi ned under directive 2011/65/eu of th e euro pean parliam e nt and of the cou n cil of june 8, 2 011 on the restriction of the use of certain hazardous s u bs tances in electrical and electronic equipment (eee) - recast, unless oth er wis e specified as n o n-compliant. please note that some vishay docum e ntation may still m ake reference to rohs directive 2002/95/ ec. we confirm that all the produ c ts identified as bein g co mp lian t t o di rect ive 2002 /95 / ec conform to directive 20 11/65/eu. vishay intertechnology, i n c. hereby certifi es that all its produ c ts that are identified as ha logen-free follow halogen - free requirements as per je dec js709a stan dards. please note that some vish ay documentation may still m ake ref e ren c e to the iec 61 249 -2-21 definition. we co nfirm that all the pr oducts identified as being compliant to iec 6 1249 -2-21 confor m to jedec js 709a standards. |
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